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TSMC Developing a 1-nm CMOS Process
Less than two weeks after IBM announced their 2-nanometer CMOS technology, UK website Verdict picked up on a paper published in Nature and somehow morphed that into a claim that TSMC had made breakthrough in 1-nm technology development. The essence of the paper is the use of bismuth (Bi) to provide contact to a molybdenum disulphide (MoS2) monolayer transistor, achieving a claimed record low contact resistance of 123 Ω µm, and a record high on-state current density of 1,135 µA/µm. The authors state that “This technology unveils the potential of high-performance monolayer transistors that are on par with state-of-the-art three-dimensional semiconductors, enabling further device downscaling.
The paper was a joint presentation from MIT, TSMC, UC Berkeley, National Taiwan University (NTU), and the King Abdullah University of Science & Technology (KAUST) in Saudi Arabia, with 23 authors in all. It was submitted on 1 July last year and published 12 May. A press release from MIT explains that one of the challenges in the use of monolayers is the contact resistance between the metal contact electrode and the monolayer and using a semi-metal such as bismuth reduces or eliminates the Schottky barrier at the contact interface. 2D monolayers “meet all the requirements for enabling a leap in miniaturization of transistors, potentially reducing by several times a key parameter called the channel length — from around 5 to 10 nanometers, in current cutting-edge chips, to a sub nanometer scale.”
TSMC has been collaborating with MIT, NTU and quite a lot of other organizations and MoS2 has been a common topic. A conventional metal contact has a Schottky barrier at the interface, where the semiconductor is heavily doped, by putting a thin dielectric layer at the interface; it is hard to dope a monolayer, and an extra dielectric layer adds a tunnelling barrier, which gives high contact resistance. The state-of-the-art contact resistance report was ~1.1 kΩ-μm, at least one order of magnitude larger than metal–Si contacts. Nickel induces gap states at the interface, creating energy barriers and high contact resistance; but bismuth is a semi-metal, and it suppresses the gap states and spontaneously forms degenerate states in the monolayer, giving zero Schottky barrier height. The next figure is a schematic of a Bi-MoS2 FET in the upper right, with the area outlined enlarged to its left and below, showing an atomic rendering; left of that is the corresponding electrostatic potential profile along the vertical direction, with the electron tunnelling barrier shaded in purple (width, wt = 0.166 nm; height, Φt = 3.6 eV). The distance between the Bi and S atomic layers d = 0.34 nm. The colored regions at the interface within the dashed line in the atomic structure indicate the differential charge density (red = +ve, blue = -ve), calculated by subtracting the pre-contact charge density from the post-contact charge density.
Less than two weeks after IBM announced their 2-nanometer CMOS technology, UK website Verdict picked up on a paper published in Nature and somehow morphed that into a claim that TSMC had made breakthrough in 1-nm technology development. The essence of the paper is the use of bismuth (Bi) to provide contact to a molybdenum disulphide (MoS2) monolayer transistor, achieving a claimed record low contact resistance of 123 Ω µm, and a record high on-state current density of 1,135 µA/µm. The authors state that “This technology unveils the potential of high-performance monolayer transistors that are on par with state-of-the-art three-dimensional semiconductors, enabling further device downscaling.
The paper was a joint presentation from MIT, TSMC, UC Berkeley, National Taiwan University (NTU), and the King Abdullah University of Science & Technology (KAUST) in Saudi Arabia, with 23 authors in all. It was submitted on 1 July last year and published 12 May. A press release from MIT explains that one of the challenges in the use of monolayers is the contact resistance between the metal contact electrode and the monolayer and using a semi-metal such as bismuth reduces or eliminates the Schottky barrier at the contact interface. 2D monolayers “meet all the requirements for enabling a leap in miniaturization of transistors, potentially reducing by several times a key parameter called the channel length — from around 5 to 10 nanometers, in current cutting-edge chips, to a sub nanometer scale.”
TSMC has been collaborating with MIT, NTU and quite a lot of other organizations and MoS2 has been a common topic. A conventional metal contact has a Schottky barrier at the interface, where the semiconductor is heavily doped, by putting a thin dielectric layer at the interface; it is hard to dope a monolayer, and an extra dielectric layer adds a tunnelling barrier, which gives high contact resistance. The state-of-the-art contact resistance report was ~1.1 kΩ-μm, at least one order of magnitude larger than metal–Si contacts. Nickel induces gap states at the interface, creating energy barriers and high contact resistance; but bismuth is a semi-metal, and it suppresses the gap states and spontaneously forms degenerate states in the monolayer, giving zero Schottky barrier height. The next figure is a schematic of a Bi-MoS2 FET in the upper right, with the area outlined enlarged to its left and below, showing an atomic rendering; left of that is the corresponding electrostatic potential profile along the vertical direction, with the electron tunnelling barrier shaded in purple (width, wt = 0.166 nm; height, Φt = 3.6 eV). The distance between the Bi and S atomic layers d = 0.34 nm. The colored regions at the interface within the dashed line in the atomic structure indicate the differential charge density (red = +ve, blue = -ve), calculated by subtracting the pre-contact charge density from the post-contact charge density.
The devices were fabricated by transferring the MOCVD or CVMoS2 monolayers from growth substrates onto silicon nitride or silicon dioxide dielectric layers on P++ Si substrates, and 20 nm bismuth was e-beam deposited and given a gold capping layer. E-beam lithography was used to define the channel and source/drain contacts, with channel lengths of ~30 – 500 nm and channel widths of 2 – 10 μm. The P++ substrate was used as a back-gate for transistor operation.
The effect of the reduced barrier can be seen in Fig. 2(a) – by plotting total device resistance vs channel length for different carrier densities (N2D), the intercept on the vertical axis (zero channel length) will be twice the contact resistance RC, giving a RC value of ~123 Ω-μm. The inset SEM image is a false color image of the test structure.
In the next figure (b) the difference between nickel and bismuth contacts is clear; the IDS – VDS characteristic of a Bi-MoS2 FET (VGS = 60V) at low temperature is linear and Ohmic, and the Ni-MoS2 FET shows the effect of the Schottky barrier.
The effect of the reduced barrier can be seen in Fig. 2(a) – by plotting total device resistance vs channel length for different carrier densities (N2D), the intercept on the vertical axis (zero channel length) will be twice the contact resistance RC, giving a RC value of ~123 Ω-μm. The inset SEM image is a false color image of the test structure.
In the next figure (b) the difference between nickel and bismuth contacts is clear; the IDS – VDS characteristic of a Bi-MoS2 FET (VGS = 60V) at low temperature is linear and Ohmic, and the Ni-MoS2 FET shows the effect of the Schottky barrier.
The next figure shows IDS – VDS curves of Bi–MoS2 FETs with channel lengths of 120 and 35 nm on 100-nm-thick SiNxgate dielectrics. The linear relationships at low-field indicate ohmic contacts, leading to high ION/IOFF current ratios (>107) and very high drive current for monolayer transistors with a drain voltage of 1.5 V. The inset is a SEM image of the 35-nm device.
The highest values of ION achieved were 560 μA/μm for the 120-nm LCH, and 1,135 μA/μm for the 35-nm LCH devices. That compares with a highest nFET current of 390 μA/μm at VDS = 1 V for a 100-nm channel in [2], although that used 10 nm HfO2 as a gate dielectric layer. The Bi contact resistance was 123 Ω µm, compared to a previously reported ~1.1 kΩ-μm, almost an order of magnitude better.
Nowhere in this work is there any mention of a 1-nm process. Finding a good low-resistance contact to a 2D monolayer is a great step forward, but it’s a long way from real product, so using a node number is pure speculation. Source: Semiconductor Digest
Nowhere in this work is there any mention of a 1-nm process. Finding a good low-resistance contact to a 2D monolayer is a great step forward, but it’s a long way from real product, so using a node number is pure speculation. Source: Semiconductor Digest