Vertical Divider
Intel Lost the Marketing War but Not the Chip Density Competition
Intel was widely criticized when they announced a delay to their 7nm fab, but much of the lay and expert “chip enthusiasts” mistakenly compared TSMC 7nm to Intel 7nm as though it’s an apples-to-apples comparison. Around 15 years ago, the “nanometer number” was a real physical measurement inside the chip. But then it became hard to decide what to measure, so companies calling their new processes with a number than was about 0.7x times the “size number” of their previous process. This was ok for the next 10 years, when the next process really was twice as dense as the previous one, like 0.7x shrink should give. But then TSMC, Samsung and Global Foundries made their “20nm” processes which simply sucked in performance because of leakage problems. and the GF 20nm process was cancelled. In order to get the leakage down, they had to switch to finfet style transistors (Intel had already switched to finfets in their “22nm” process).
When TSMC introduced finfet transistors, it used the same “20nm” process, but it performed like the “20nm” process should have performed. When Samsung and GF introduced their (commonly-developed) finfet process, it shrank some measurement slightly, it was almost as big as their “20nm” process. But because these “fixed 20nm finfet processes” were much better (in performance, not density) than the sucky original “20nm” processes they were replacing, they decided to call them “16nm” (TSMC) and “14nm” (GF and Samsung).
When they made their next process, which might have “deserved” the name of “14nm” or “16nm” based on their density, they called it “10nm”. And the next one got name “7nm”. But the density did not increase by a factor of 2x like it should have been, 7nm process should be 5.3 times more dense than 16nm process (16/7)^2 = 5.3, but in reality, the TSMC “7nm” process is only 3.1x more dense than TSMC’s “16nm”, which only deserves a “20nm” categorization based on density.
In reality, Intel’s “7nm” process is smaller than TSMC’s “5nm” process. Currently TSMC is reliably mass-producing huge amount of chips with 40nm metal pitch, using 193nm DUV equipment with multi-patterning, while Intel is manufacturing smaller amount of chips with 36nm metal pitch with similar 193nm DUV equipment with more aggressive multi-patterning, and not getting as high clock rates from them as it wants. And because Intel is not getting high enough clock speeds from this process, Intel also keeps manufacturing desktop chips with their older “14nm” process which has 52nm metal pitch.
The so-called “10nm” Intel is now using in the latest mobile chips is actually slightly smaller than TSMC’s manufacturing process called “7nm”; The most important measurement of a chip is the pitch of two metal wires. This is 40nm for the TSMC “7nm” process but 36nm for intel’s “10nm” process.
The main reasons why Intel’s “10nm” process was late include:
And Intel’s “7nm” is mostly late because they had to get their “10nm” working first. Many of the engineers that were supposed to be developing the “7nm” process were working on fixing the “10nm” instead. And there were probably some things in the “7nm” process which were supposed to be based on the “10nm” process, when the “10nm” process had not stabilized they could not just take them from there.
Intel’s “7nm” process should be in production in 2023, and will be denser than TSMC’s “5nm” process, but TSMC might already have their “3nm” process out by then. TSMC’s “3nm” might be slightly, but not much denser than Intel’s “7nm”.
Intel is still utilizing a monolithic architecture. AMD has gotten around the yield problem by designing their ‘Infinity Fabric’ interconnect between ‘chiplets’. AMD is getting 80% plus yields per wafer at 7nm, while intel could not break 50% (43% in the last report I saw) in their 10nm effort. Wasting 1/2 of a very expensive wafer is not a viable strategy. Intel needs an answer for Infinity Fabric before they can effectively produce at a smaller node. AMDs “Renoir” chip (4000-series mobile chips and 4000G-series desktop APUs) is a 156mm^2 monolithic chip, with 8 CPU cores and 8 GPU cores.
The monolithic vs chiplets yield is mostly about server chips, Ice Lake SP server chip will be around 400mm , versus AMDs 8 * 78mm of “7nm” + 416mm^2 of “14nm” of Rome. From: Global Foundries/Samsung “14nm” process. Heikki Kultala Technical leader, SoC architecture at Nokia (company) (2020–present)
TSMC has held a ceremony marking the completion of the plant structure for its 3nm fab at the Southern Taiwan Science Park (STSP). The foundry house is expected to kick off commercial production at the 3nm fab in 2022. In the semiconductor backend sector, quotes for processing memory applications have gone up to reflect rising material costs. For Taiwanese researchers, they will have free access to ArmIPs, thanks to an agreement signed between the vendor and the Taiwan Semiconductor Research Institute (TSRI).
A separate report indicated TSMC 3nm fab nears completion: TSMC has held a topping-out ceremony for a new 3nm fab at its manufacturing base at the Southern Taiwan Science Park (STSP), paving the way for the new facility to kick off commercial production in the second half of 2022.
Intel was widely criticized when they announced a delay to their 7nm fab, but much of the lay and expert “chip enthusiasts” mistakenly compared TSMC 7nm to Intel 7nm as though it’s an apples-to-apples comparison. Around 15 years ago, the “nanometer number” was a real physical measurement inside the chip. But then it became hard to decide what to measure, so companies calling their new processes with a number than was about 0.7x times the “size number” of their previous process. This was ok for the next 10 years, when the next process really was twice as dense as the previous one, like 0.7x shrink should give. But then TSMC, Samsung and Global Foundries made their “20nm” processes which simply sucked in performance because of leakage problems. and the GF 20nm process was cancelled. In order to get the leakage down, they had to switch to finfet style transistors (Intel had already switched to finfets in their “22nm” process).
When TSMC introduced finfet transistors, it used the same “20nm” process, but it performed like the “20nm” process should have performed. When Samsung and GF introduced their (commonly-developed) finfet process, it shrank some measurement slightly, it was almost as big as their “20nm” process. But because these “fixed 20nm finfet processes” were much better (in performance, not density) than the sucky original “20nm” processes they were replacing, they decided to call them “16nm” (TSMC) and “14nm” (GF and Samsung).
When they made their next process, which might have “deserved” the name of “14nm” or “16nm” based on their density, they called it “10nm”. And the next one got name “7nm”. But the density did not increase by a factor of 2x like it should have been, 7nm process should be 5.3 times more dense than 16nm process (16/7)^2 = 5.3, but in reality, the TSMC “7nm” process is only 3.1x more dense than TSMC’s “16nm”, which only deserves a “20nm” categorization based on density.
In reality, Intel’s “7nm” process is smaller than TSMC’s “5nm” process. Currently TSMC is reliably mass-producing huge amount of chips with 40nm metal pitch, using 193nm DUV equipment with multi-patterning, while Intel is manufacturing smaller amount of chips with 36nm metal pitch with similar 193nm DUV equipment with more aggressive multi-patterning, and not getting as high clock rates from them as it wants. And because Intel is not getting high enough clock speeds from this process, Intel also keeps manufacturing desktop chips with their older “14nm” process which has 52nm metal pitch.
The so-called “10nm” Intel is now using in the latest mobile chips is actually slightly smaller than TSMC’s manufacturing process called “7nm”; The most important measurement of a chip is the pitch of two metal wires. This is 40nm for the TSMC “7nm” process but 36nm for intel’s “10nm” process.
The main reasons why Intel’s “10nm” process was late include:
- They tried to improve too much at once. TSMC and Samsung no longer try to make their new processes 2x denser and simply just cheat on their marketing nanometer numbers, while Intel tried to make a process that’s about 2.2x denser than their previous “14nm” process. It’s much easier to make small changes than big changes.
- They tried to make very small features with big 193nm wavelength equipment with very aggressive multi-patterning. TSMC is not having as small features in its “7nm” process, Samsung is not having as small features in its “8nm” process and both are moving to 13.5nm EUV equipment to manufacture so small features (Samsung in their “7nm” process, TSMC in their “7nm+”, “6nm” and “5nm” processes). Intel is only moving to 13.5 EUV equipment with their “7nm” process which will then be smaller than TSMCs “5nm” process.
- They introduced some interconnects made from cobalt. New materials are always risky.
And Intel’s “7nm” is mostly late because they had to get their “10nm” working first. Many of the engineers that were supposed to be developing the “7nm” process were working on fixing the “10nm” instead. And there were probably some things in the “7nm” process which were supposed to be based on the “10nm” process, when the “10nm” process had not stabilized they could not just take them from there.
Intel’s “7nm” process should be in production in 2023, and will be denser than TSMC’s “5nm” process, but TSMC might already have their “3nm” process out by then. TSMC’s “3nm” might be slightly, but not much denser than Intel’s “7nm”.
Intel is still utilizing a monolithic architecture. AMD has gotten around the yield problem by designing their ‘Infinity Fabric’ interconnect between ‘chiplets’. AMD is getting 80% plus yields per wafer at 7nm, while intel could not break 50% (43% in the last report I saw) in their 10nm effort. Wasting 1/2 of a very expensive wafer is not a viable strategy. Intel needs an answer for Infinity Fabric before they can effectively produce at a smaller node. AMDs “Renoir” chip (4000-series mobile chips and 4000G-series desktop APUs) is a 156mm^2 monolithic chip, with 8 CPU cores and 8 GPU cores.
The monolithic vs chiplets yield is mostly about server chips, Ice Lake SP server chip will be around 400mm , versus AMDs 8 * 78mm of “7nm” + 416mm^2 of “14nm” of Rome. From: Global Foundries/Samsung “14nm” process. Heikki Kultala Technical leader, SoC architecture at Nokia (company) (2020–present)
TSMC has held a ceremony marking the completion of the plant structure for its 3nm fab at the Southern Taiwan Science Park (STSP). The foundry house is expected to kick off commercial production at the 3nm fab in 2022. In the semiconductor backend sector, quotes for processing memory applications have gone up to reflect rising material costs. For Taiwanese researchers, they will have free access to ArmIPs, thanks to an agreement signed between the vendor and the Taiwan Semiconductor Research Institute (TSRI).
A separate report indicated TSMC 3nm fab nears completion: TSMC has held a topping-out ceremony for a new 3nm fab at its manufacturing base at the Southern Taiwan Science Park (STSP), paving the way for the new facility to kick off commercial production in the second half of 2022.
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Barry Young
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